1. Field of the Invention
The present invention relates to a high speed data communications system and in particular to a transceiver mounting arrangement for such a system.
2. Description of the Prior Art
In high speed data communications systems using computers it is recognized that the electrical characteristics of the signal paths, or "buses", interconnecting various circuit modules of the system become increasingly critical as transmission rates increase and as logic transition times decrease. These buses, whether realized as traces on a circuit board, coaxial cables, twisted pairs or individual wires, must be considered as transmission lines. To achieve error-free, high speed digital transmission the transmission lines must exhibit certain properties: uniform characteristic impedance (which requires uniform geometry) along their length; optimum characteristic impedance consistent with current sourcing capability of the driving circuit elements; proper terminations at the ends to prevent reflections; and high propagation velocity.
In the typical system the main system bus is disposed on a bus support substrate called a "motherboard" and the constituent modules of the system are disposed on separate dedicated support substrates, or "daughterboards". The overall data processing system is configured by physically interconnecting the daughterboards with the motherboards. The requisite properties of the main bus on the motherboard are adversely affected when daughterboards are removed from or added thereto.
In an attempt to minimize effects on the properties of the main bus, high input impedance transceivers are located on the daughterboard near the point at which it is received by the motherboard. However, the transceiver itself, as well as the "stub" or branch conductor through which the transceiver is interconnected to the bus, imposes non-negligible impedance and capacitive loads on the bus. These loads tend to change the properties of the bus when daughterboards are added or removed. For example, when daughterboards are present the effective impedance of the bus is lowered. Accordingly, precise termination of the bus (necessary to prevent signal reflections) is difficult to maintain.
Changes in the bus impedance caused by the absence or presence of transceivers along a bus are addressed by U.S. Pat. No. 4,475,191. In accordance with this patent where daughterboards are present the bus is terminated in a first impedance. Where the daughterboards are absent the bus is terminated in a second, higher, characteristic impedance. In addition a current driver with a deliberately lengthened rise time is used. Such a solution to the impedance matching problem, however, imposes limitations on the speed of operation and upon the transition time between logic levels.
The impedance and capacitive loads imposed on the bus by the stubs is recognized in the Motorola MECL Design Handbook. This reference work defines limitations on bus properties in relation to the number and length of the stubs and places upper limits on the length of the stubs in order to hold the effects of the stubs within tolerable limits.
In the related technology of local area networks, as typified by the Ethernet (.TM.) network, the properties of the coaxial cable bus used therein are maintained as constant as possible by utilization of transceivers mounted in cable tap units which are attachable along the bus. In such systems the transceivers are typically contained within the cable tap unit and are connected to the coaxial cable at designated locations by means of an insulation piercing connector arrangement. When the cable tap unit is removed the transceiver and connector are removed as well.
In view of the foregoing it is believed advantageous to provide a communications bus that exhibits precisely determinable impedance and time delay characteristics and that maintains these characteristics regardless of the presence or absence of associated circuit modules connected to the bus at all of the transceiver arrays provided for that purpose.